One of the most difficult challenges facing semiconductor vendors is the physical interconnections and terminations necessary for IC's to "talk" to the outside world. With integrated circuit technologies already in the sub-micron range it is common to see a complete computer fabricated on a single piece of silicon less than 0.3 inches square. As more functions are packed onto these IC's, the cost per function decreases. In fact, silicon IC's have become so cheap that the cost of the final product is dominated by complex interconnecting components. Interconnecting components, however, provide very little added value to the product, and greatly reduce electrical performance due to inherent capacitances, inductances and mismatched termination impedances.
A printed circuit board is commonly used to connect semiconductor components and other electrical parts. A typical personal computer can include as many as 100 integrated circuits, plus a number of discrete components such as crystals, capacitors and switches, all linked together on one or more printed circuit boards. Many of these IC's are individual, multi-pin IC's employing six to as many as 120 interconnection pins.
Each individual IC is packaged in a highly sophisticated packaging solution that "brings out" signal lines measured in millionths of an inch on the IC to external pins measured in tenths of an inch. When these signals reach another IC, they are again de-magnified to millionths of an inch dimensions. As a signal passes from one IC to another on a typical printed circuit board, this sequence is repeated many times. With the number of IC's included on a printed circuit board increasing, these magnification and demagnification techniques become costlier, making the IC's harder to produce and as a result more unreliable. Moreover, this interconnection approach is used for virtually all integrated circuits today. Thus, regardless of how small the IC itself becomes, interconnection requirements remain a major obstacle to smaller, and less expensive products.
Efforts have been made to simplify the interconnection schemes for integrated circuits. The goal has been to achieve the highest packing densities possible, i.e., to include the most functions or IC's on a printed circuit board. Modern solutions include the use of multi-layer printed circuit boards, high density connectors, and narrow line flexible circuitry. These techniques, however, are costly and have factors that limit overall performance.
Some of the more advanced techniques developed include multi-layer ceramic substrates, complex hybrids of silicon and ceramics, and multi-chip-module three-dimensional IC integration. Such techniques can achieve very fast electrical performance, but command a very high price. Thus, they are generally limited to applications where improvements in speed outweigh concerns over cost.
Since consumer demand for lighter, smaller and less costly products continues to be a driving force for new technology, an IC interconnection technique that can pack the greatest silicon horsepower into the smallest volume and at the lowest cost will present a substantial advantage over the prior art. One method of achieving greater functional integration without significantly impacting price or performance requirements would be to eliminate as much of the packaging surrounding each IC as possible. Attempts along these lines have been made, but each has its own disadvantages.
Chip-on-board is a technique where a single silicon die is directly mounted to a printed circuit board using conductive epoxy. A silastic coating is placed over the site to protect the chip-on-board structure from external contamination. Wire bonding, however, is required to electrically connect the silicon die to the printed circuit board. This packaging approach is highly efficient and very inexpensive, but has significant size limitations that prevent many chips from being simultaneously connected to a single printed circuit board.
Tape carrier bonding is another such attempt. This technique uses a patterned one-piece flex circuit that replaces individual bond wires and allows all of the bond wires for an IC to be connected in one operation. The process, however, requires costly machinery and has found limited popularity. In addition, other compromises have restricted tape carrier bonding to smaller IC packages.
Flip-chip bonding is a technique where bonding wires have been completely eliminated. In this process, a barrier metal (typically gold or solder reflow) is first plated over the bonding pads of a particular IC die. The die is then inverted and positioned face down on top of reciprocal bonding pad patterns located on a ceramic printed circuit board. A special backside viewing machine, which uses infrared light to "look" through the silicon, is used to precisely align the die to the ceramic board. Infrared heating is then applied to fuse the solder reflow situated between the chip and the ceramic printed circuit board. This technique eliminates bonding wires, but is highly labor intensive and therefore quite costly.
It would, therefore, be advantageous to have an IC interconnection technique that eliminates bonding wires and self-contained packaging solutions, which can be employed at low cost and with minimal effort. Such a technique would connect one IC directly to another IC, and would align the two without highly labor-intensive, expensive machines.